ASIC design
We have very strong and wide experience from ASIC design starting from system and architectural design, and expanding that to both front-end and back-end design flows. Our engineers can handle a wide range of different tasks during the project.
- Low power design
- Architectural design
- Gated clocks, clocking
- DVFS
- Power management
- Power domain structures
- Power analysis
- SoC design
- Design partition
- Clocking and resetting for SoC (System on Chip)
- Block design
- DFT (Design for testability)
- Formal verification
- Synthesis, constraint generation
- Timing closure, Static timing analysis (STA), floorplan supervision
- Design verification
- High level synthesis
- Design maturity
- Interfaces
- High speed serial interfaces (SerDes)
- DDR, QDR, RLDRAM, FCRAM
- PCI and PCI-E
- Emulation
- Fast prototyping with structured ASICs
- Rapid prototyping platforms
- Custom FPGA boards
"We have a deep understanding about the whole ASIC design process."