Services

Expert in your design flow

Uninord has strong experience from Ethernet based IP network devices and wireless low power design. The experience is built on both network and mobile device development projects. We have a deep understanding about the whole product design process and we can deliver you the whole design project based on both ASIC, NPU or FPGA, with software and hardware included.

For low-power design we know how to divide the design into different power domains with hundreds of gated clock domains, how to make those and how to make the software for that. And we know how to get the most benefit of all this.

For design creation Uninord has developed own design component library called UToolLibrary. Ready designed and tested components will shorten the design time for the project and the results will be more predictable. Components are targeted to be area optimized and low power.

The working model can be settled to confirm your needs. We can operate as an independent project group or as a part of your project group. The work will be done either in-house or on-site. We have up-to-date knowledge of the latest tools and of low power technologies in ASIC, FPGA, NPU and software development.

"It is important that the implementation team is able to understand the system architecture and the motivation behind the decisions made elsewhere. This will accelerate the implementation work, reduce the risk of defects and misunderstandings and may enable new solutions and inventions."

  • System requirements
  • Standards
    • RFC, ITU, IEEE, ETSI, 3GPP, OBSAI
  • HW/SW architecture and partitioning
    • Interfaces both internally and externally
  • HW/SW architecture and partitioning
  • Performance and power analysis
  • Networking
    • Ethernet and IP networking:
      • L2/L3 level
      • IPv4, IPv6
      • MPLS, VPLS, VRF
      • Traffic Management
        • QoS
        • Packet policing, scheduling and forwarding
  • Low power design
    • Architectural design
    • Gated clocks, clocking
    • DVFS
    • Power management
    • Power domain structures
    • Power analysis
  • SoC design
    • Design partition
    • Clocking and resetting for SoC (System on Chip)
    • Block design
    • DFT (Design for testability)
    • Formal verification
    • Synthesis, constraint generation
    • Timing closure, Static timing analysis (STA), floorplan supervision
    • Design verification
    • High level synthesis
    • Design maturity
  • Interfaces
    • High speed serial interfaces (SerDes)
    • DDR, QDR, RLDRAM, FCRAM
    • PCI and PCI-E
  • Emulation
    • Fast prototyping with structured ASICs
    • Rapid prototyping platforms
    • Custom FPGA boards
  • System design for platforms using EZchip NPUs
  • NPU microcode implementation
  • NPU driver sw implementation
  • Platform verification
  • We offer completely out-sourced development projects including
    • Project and quality management
    • Architectural design and specification
    • Product feasibility studies: cost analysis, trade-off's, feature sets
    • All development work including the tools and infrastructure
  • Large experience from different applications, FPGA technologies and design
    • All major vendors
    • Specification, design & verification
    • Network and wireless protocols
    • Clocking and resetting
    • Place and Route
    • Testing
    • Emulation
      • Rapid prototyping platforms
      • Custom FPGA boards
  • SW architecture
  • Platform design
  • Application software
  • With or without OS
  • Hard real time systems
  • One-wire technology for security applications
  • Ultra-low-power processors
  • Embedded software for CPUs in FPGAs
  • ASIC and FPGA HW driver software
    Register chart to RTL generation
    Component library:
  • DSP Filter path creation
    • Channel filter
    • Interpolation filter
    • Decimation filter
    • Multistage filtering
    • DDS
    • FFT
    • Matlab models
  • Special component
    • FIFOs
    • RAM components
  • HSPA hardware accelerator
    • STA and timing closure
    • Formal verification
    • DFT
    • Power management
    • System level verification
  • Prototyping
    • Structured ASIC
    • Rapid prototyping platforms
    • Custom FPGA boards
  • Video codec design
  • LTE hardware accelerator
    • STA and timing closure
    • DFT
    • Vendor IP modules handling
  • Multi core processor
    • System level verification
  • HW-design
  • Board level simulations
  • Base station system level verification
  • OBSAI interface module design
  • System Design:
    • RFC
    • HW/SW architecture
    • L2/L3 level specification
  • ASIC and FPGA design
    • L2/L3
    • Protocol stack handling
      • Ethernet
      • IPvX
    • Flow control
      • Traffic management
      • Traffic classification
      • Hierarchical policing and shaping
    • Interfaces
      • POS-PHY, IX-bus
      • SerDes
      • DDR, QDR, RLDRAM, FCRAM
      • PCI and PCI-E
    • Prototyping with custom FPGA boards
    • Synthesis
    • STA and timing closure
    • Formal verification